1. Field of the Invention
The present invention relates to an apparatus for decoding, through expansion, a moving picture signal compressed through two-dimensional picture compression, in particular, by a data compression technology using an interframe prediction as in the so-called MPEG system.
2. Description of Related Art
The data compression conforming to the so-called MPEG/Video (will be referred to as xe2x80x9cMPEGxe2x80x9d hereinafter) being the international standard for the moving picture compression, involves three types of frames (pictures) which will be described below. One of them is an I-picture (intra-code picture). This frame is not interframe predicted but compressed within itself. Therefore, the I-picture can be decoded requiring no data of any other frame. Other two frames are P-picture and B-picture. The P-picture is a predictive-coded picture, and B-picture is a bidirectionally predictive-coded picture. The P-picture is decoded through forward prediction from an I- or P-picture existing before the P-picture or frame in consideration. The B-picture is decoded through backward prediction from a frame existing after the frame in consideration in addition to forward prediction from an I- or P-picture existing before the frame in consideration. That is, the B-picture can be decoded through any of the forward, backward and bidirectional predictions. The MPEG referred to herein stands for the Moving Picture-coding Experts Group of the ISO/IEC JTC/SC29 (International Organization for Standardization/International Electrotechnical Commission, Joint Technical Committee 1/Sub Committee 29). The MPEG-1 (MPEG phase 1) standard includes ISO 11172, and the MPEG-2 standard includes ISO 13818. In these international standards, ISO 11172-1 and ISO 13818-1 are included in the item xe2x80x9csystem multiplexingxe2x80x9d, ISO 11172-2 and ISO 13818-2 are included in the item xe2x80x9cvideo codingxe2x80x9d, and ISO 11172-3 and ISO 13818-3 are included in the item xe2x80x9caudio codingxe2x80x9d.
FIG. 1 shows an example of the dependency of the above three types of frames I, P and B upon each other.
In FIG. 1, frames (pictures) are indicated with references I1, B2, B3 and P4, respectively, numbered from the left to right. As mentioned above, xe2x80x9cIxe2x80x9d means an intra-coded picture, namely, I-picture, xe2x80x9cPxe2x80x9d indicates a predictive-coded picture, namely, P-picture, and xe2x80x9cBxe2x80x9d indicates a bidirectionally predictive-coded picture, namely, B-picture. The arrows indicate directions of prediction, respectively. I1 is an I-picture numbered one, and decoded within itself. P4 is a P-picture numbered four. For decoding this frame, it is necessary to use a motion vector for reading the result of I1 frame decoding for calculation. B2 is a B-picture numbered 2. It is decoded through bidirectional prediction. For image restoration, an interframe prediction (that is, motion compensation) is done based on the results of I1 frame decoding and P4 frame decoding.
FIG. 2 shows, along the time base, necessary data for decoding frames of the above types.
In FIG. 2, data of the frame I1 is required for decoding itself as well as for motion compensation (MC) for each of the frames B2, B3 and P4. For decoding B-pictures including the frames B2, B3, etc., data of the frame P4 is required in addition to the data of the B-pictures themselves. The frame P4 being a P-picture is necessary for decoding the frames B2, B3, P4, B5 and B6 as shown in FIG. 2. The I-picture and P-picture required for decoding the B-pictures should have been decoded before the B-pictures are decoded, and should be held all the way through the decoding of the B-pictures. As seen from FIG. 2, data for up to three frames including the B-picture have to be held at a time. The buffer memories for holding these frames should have a large storage area. Therefore, they are used as external memories incidentally to the decoder.
FIG. 3 shows an example of the time of decoding in the actual MPEG decoder.
In FIG. 3, a time of decoding is indicated with a reference T1 while a time of presentation is indicated with a reference T2. In this example, a time gap between the decoding and presentation equivalent to 1.5 frames for I-picture (as indicated with T3 in FIG. 3), and 0.5 frame for B-picture (as indicated with T4). As seen also from FIG. 2, the result of I1 decoding in FIG. 3 is not only required for decoding the I1 frame, but for decoding the frames P4, B2 and B3, and so should be held for the time of their decoding. The P4 frame is necessary for presentation of the frame P4 itself and decoding of frames B2, B3, P7, B5, etc., and so held for the time of their decoding. The B-pictures are held either by buffering one frame or by holding only a part thereof, any of which will require a large memory area.
FIG. 4 shows an example of the conventional MPEG decoder configuration.
In FIG. 4, an MPEG bit stream is supplied to an MPEG decoder 7 at a terminal 6 thereof. Then, it is first decomposed by a demultiplexer 8 into audio and video bit streams. The bit streams are passed over a signal line 9, bus 10 and signal line 11, and written once into an area 14 of an external memory 13 via a memory interface circuit 12. There is shown a signal line 15 which represents a data bus, address signal line, etc. laid between the decoder 7 and external memory 13. Note that a block for processing audio signals is not shown in FIG. 1.
The video bit stream read from the area 14 of the external memory 13 is passed through the memory interface circuit 12, signal line 11, bus 10 and a signal line 16 to a video decoder 17.
The video decoder 17 comprises mainly a header/VLD circuit 18 for analysis of header and variable-length code, inverse quantizer (IQ; also dequantizer) 19, inverse discrete cosine transformer (IDCT) 20, motion compensator (MC) 21, etc.
The motion compensator 21 is supplied via a signal line 22 with a reference image read using the motion vector and reconstructs or restores it. The reconstructed or output image from the motion compensator 21 is passed through a signal line 23, bus 10, signal line 11 and memory interface circuit 12, and written into an area in the external memory 13. For example, a decoded I-picture, P-picture and B-picture are written into designated areas 24, 25 and 26, respectively, in the external memory 13. Each of these areas should have a size for one frame. The external memory 13 should have a rather large size. Note that the area 24 for the I-picture is also available for the P-picture.
The data of the I-picture in the external memory 13 is read at the time of presentation in FIG. 3, passed to an image display circuit 28 over a signal line 27, and delivered as an image data at a terminal 29. Also, the data of the I-picture in the external memory 13 is also read for decoding the B- or P-picture at the time shown in FIG. 3. The data of the P-picture is similarly read for presentation and also for decoding of the B-picture. In FIG. 4, the B-picture is shown written in one-frame area in this example. It is read from this area at the time of presentation shown in FIG. 3.
The aforementioned MPEG system combines together a variety of data compressing techniques to implement a high quality and compressibility of the video compression. The interframe prediction is one of the most important techniques. In the interframe prediction system, a motion vector is used to extract a block most approximate to a block being currently decoded from a frame existing before or after the frame in consideration, calculate a difference between the blocks and compress the result of the calculation. To decode a bit stream compressed through the interframe prediction, however, a frame data having previously been decoded should be held, which will require an increased memory capacity.
More particularly, the above-mentioned example of the conventional MPEG decoder needs to store decoded image data for at least 3 frames. This image data storage requires an external memory 13 having a large area. For a main level (ML) decoder according to MPEG, for example, required is an external memory 13 having a capacity of about 16 Mbits, and thus a large chip area is required for integration of the memory into the chip. These requirements will lead to a considerably large increase of manufacturing costs. Furthermore, for a high-level (HL) decoder conforming to MPEG, the frame size is 4 to 6 times larger and the necessary memory size is very large. For implementing the HL decoder with an external memory 13, the band width of a bus between the decoder 7 and external memory 13 is a problem. For integration of the memory into a chip, the chip area should be large. Therefore, such a decoder is difficult to implement with the prior art.
Accordingly, the present invention has an object to overcome the above-mentioned drawbacks of the prior art by providing a compressed moving picture signal decoding apparatus adapted to effectively function with a reduced bus band width as well as with no increase in memory capacity, chip area for integration of the memory into the chip and manufacturing costs.
The above object can be accomplished by providing a compressed moving picture signal decoding apparatus in which according to the present invention, a moving picture signal compressed through interframe prediction, a data resulted from decoding a compressed moving picture signal to block level is compressed on the unit of blocks, an address information of the data compressed and written into a memory is held block by block, the compressed data in the memory is read and expanded block by block, a necessary compressed data is read from the memory and expanded at the times of actual presentation and motion compensation, and used the data for the actual presentation and motion compensation.
More particularly, according to the present invention, a decoded data to be used later is compressed again by any other method and expanded when necessary to reduce the necessary memory capacity. In other words, frame data to be stored into the memory is compressed once, and read later when necessary for use in presentation or motion compensation. Hence, the memory size for holding the frame data is considerably reduced, the memory can be integrated into a chip, and also it is possible to accommodate a large number of pixels in the frame data without the necessity of increasing the memory size.